1. Field of the Invention
The present invention relates to a voltage monitoring circuit including a differential amplifier circuit and a buffering circuit formed by complementary metal oxide semiconductor (CMOS) inverters, and more particularly, to the improvement of the buffering circuit.
2. Description of the Related Art
A first prior art voltage monitoring circuit includes a differential amplifier circuit for receiving an analog input voltage and a reference voltage to generate an output voltage, and also includes a buffering circuit formed of two CMOS inverters in series for receiving the output voltage of the differential amplifier circuit to output a digital output voltage. This will be explained later in detail.
In a first stage of the CMOS inverters, if the high level of an input voltage is not sufficiently high, both of a P-channel MOS transistor and an N-channel MOS transistor of the first stage CMOS inverter are in an ON state, so that an ON-On current or a through current flows through the first stage CMOS inverter, which increases the power dissipation.
In order to reduce the above-mentioned through current, the gate lengths of the transistors of the first stage CMOS inverter are made larger, to suppress the current ability of the transistors.
In the first prior art voltage monitoring circuit, if the gate lengths of the transistors are made larger, the sizes of the transistors are increased, which increases the input capacitance of the first stage CMOS inverter. As a result, the response speed is reduced.
In a second prior art voltage monitoring circuit (see JP-A-6-152341), a diode-connected N-channel MOS transistor and a P-channel MOS transistor are connected between a power supply terminal and the first stage CMOS inverter. The P-channel MOS transistor is controlled by the output voltage of the voltage monitoring circuit. That is, when the output voltage is low, the voltage at the power supply terminal is applied to the first stage CMOS inverter. On the other hand, when the output voltage is high, a voltage lower than the voltage at the power supply terminal is applied by the diode-connected MOS transistor to the first stage CMOS inverter. This will also be explained later in detail.
Thus, in the second prior art voltage monitoring circuit, since the gate lengths of the transistors of the first stage CMOS inverter do not need to be larger, the input capacitance of the first stage CMOS inverter can be reduced, which increases the response speed.
In the second prior art voltage monitoring circuit, however, if the voltage at the power supply terminal is too low, a through current may still flow through the first stage CMOS inverter, which increases the power dissipation.